Digital subtractor with means for providing conjugate angle



United States Patent Willlam R. Reader Ottawa, Ontario, Canada [21] AppLNo. 650,682 1 [22] Filed July/3,1967

[45] Patented Dec. 8, 1970 173] Assignee Northern Electric Company Limited Montreal, Quebec, Canada 72] Inventor [54] DIGITAL SUBTRAC'IOR WITH MEANS FOR PROVIDING CONJUGA'IE ANGLE 6Clalms,lDraw1ngFlg.

521 11.5.0. 235/177, 235/174; 340/1462; 343/766 51 161. c1. o06r7/02, G061 7/385, G06f 15/20 501 FleldofSearch 235/174, 177; 343/757, 760, 763, 766; 340/347A/D, 146.2

[56] References Cited UNITED STATES PATENTS 2,953,773 9/1960 31166161116616 23s/177x 2,954,928 10/1960 Davey 1/1962 Andrews FOREIGN PATENTS 362,736 8/1962 Switzerland Primary Examiner-Malcolm A. Morrison Assistant Examiner-R. Stephen Dildine, Jr. Attorney-Weir, Marshall, MacRae & Lamb ABSTRACT: A digital subtractor, primarily for use in an antenna azimuth control system, which produces the conjugate angle (360 complement) when necessary for most efficient control. A fixed bias is added to the input signals so that the resulting error signal is always positive. Any excursion of the error signal beyond the range 0 359 is detected and an additional bias signal of 360 added or subtracted to restore the error signal to the range 0 359.

DIGITAL SUBTRACT OR WITH MEANS FOR PROVIDING CONJUGATE ANGLE BACKGROUND OF THE INVENTION This invention relates to a digital subtractor for numbers representing angles which gives the conjugate (or 360 complement) when the difference of the angles lies outside the range I 80 to 180.

- One major use of this form of subtractor is in systems controlling the azimuth direction of a steerable antenna. In such a system the position of the antenna at any time is compared with the commanded position. The difference represents the position error at that time, and this signal is fed to the servodrive system which then acts to correct the antenna position in such a way as to bring the error signal to zero.

In a digital control system for such antennas the commanded position and the antenna position are represented by digital signals in some code, usually binary. In azimuth these digital signals represent angles in the range 359 with a resolution depending upon the application. Since both the commanded position and actual position can be at any angle, the difference between their digital signals may exceed 180. If the antenna is to rotate through the minimum angle then it is necessary to take the conjugate (or 360 complement) angle of error angles greater than 180 to obtain the absolute angular difference.

It is known to obtain the conjugate angle by applying a fixed 360 signal to one input of a digital subtractor and the angle of which the conjugate isto be taken to the other input. Clearly, this requires the continual use of an additional subtractor together with appropriate control means or else, in a general purpose digital computer, the use of such an additional subtractor on a programmed basis. I

SUMMARY OF THE INVENTION The digital subtractor of this invention includes subtraction means for obtaining the difference of two digital input signals representing angles. A fixed bias is added to the subtraction means so that if the conjugate operation is not required the resulting error signal falls within a preselected range. Detectors are provided to sense when the error signal falls outside single digital subtractor can be used with simple modifications to perform both the normal subtractionoperation and the conjugate angle forming operation.

BRIEF DESCRIPTION OF THE DRAWING DESCRIPTION OF THE PREFERRED EMBODIMENT The digital subtractor shown in the drawing receives an antenna positions (a) Y 10, (b) Y 200 and (0) Y 280. The resulting differences are (a) 50" (b) l 40 and (c) 22 0 with positive differences requiring clockwise rotation of the antenna and negative differences anticlockwise rotation. Most efiicient performance requires that in condition (0) the antenna should not rotate 220 in an anticlockwise direction but should instead rotate 140 in a clockwise direction. Hence the subtractor should be capableof forming the conjugate (or 360 complement) of the difference angle when it exceeds l80 and at the same time changing the indicated direction of rotation.

When the operation of forming the conjugate angle has been carried out the output or error signals will lie in the range l80 to 180. In the described embodiment a fixed bias of 180 is added to the subtractor so that the output signal is always above zero. Thus the output signal E lies in the range 0- --359 with an implicit reference point at 180. Values in the range l80-359 show clockwise rotation of the antenna is required and values in the range 0--l79 show anticlockwise rotation is required. It will be clear to those skilled in the art that a suitable control system having a reference input corresponding to 180 and the other input connected to the output of the subtractor will perform the required function of driving the antenna to the correct position.

In the condition when 1s0sX-Ys1s0 no conjugate operation is required in regard to the difference angle and the subtractor is required to produce an output signal E given by the relationship E= X- Y+ 180 (2) In the condition when 1so X- Y the subtractor output signal is given by E=X-Y- 180 (4) In the remaining possible condition when X- Y 180 j the subtractor output signal is given by ltwill be realized that, apart from the fixed bias of l80, equations 4 and 6 implicitly contain the conjugate operation.

In the digital subtractor shown in the drawing the units subtraction is carried out by an analogue comparator I0 controlling the operation of a reversible decade counter 11 which is responsive to clock pulses from a source 12 via a conductor 15. Comparator 10 has weighted inputs connected to the four hits of X, the four bits of Y, and, via conductors 16, the four bits of the output signal E,. When E, is less than X, Y, a

input signal X representing the desired azimuth position of a member such as an antenna (not shown) and a further input signal Y representing the actual antenna position. X and Y can have any value in the range 0359 and are each represented in binary coded decimal (B.C.D.) notation with X, Y, representing the units digits, X,0 Y 0 the tens digits and X Y,. the hundreds digits. Since neither X nor Y canexceed 3 only two bits are necessary to represent each hundreds digit.

Clearly, a simple subtraction operation X y will supply incount-up signal is given on conductor 13 and counter 11 is incremented by one on each clock pulse until the count-up" signal is removed. When E, is equal to X, Y, the count-up? signal is removed and E, has assumed the correct value. A

delay is incorporated in comparator 10 to maintain the count-up" signal while the count in decade counter 11 is changing. When E, is greater than X, Y, then-a count down signal is applied to the counter via conductor 14 so that the count decreases until E, assumes the value X, Y,.

An almost identical arrangement is provided for the tens digits consisting of a comparator 20 controlling a reversible decade counter 21 via a count-up" conductor 23 and a count-down conductor 24. Counter 21 receives clock pulses via a conductor 25 and its output signal E,0 is fed back to the comparator input via conductors 26. Comparator 20 has weighted inputs connected to the four bits of X,0, the four bits of Y,0 and the four bits of E,0 and functions to produce a count E equal to X Y A borrow system is necessary between the units and tens counters and is provided by a flip-flop 18 having its SET and RESET terminals connected to counter 11 via conductors 17 and 19 respectively. When flip-flop 18 is SET its output condu'ctor 22 is energized to add a weighted count of to the units comparator and to subtract an identical count from the tens comparator. This situation occurs when X, is less than Y, and, hence, counter 11 counts down to zero. At the next clock pulse the count changes from O to 9 and a borrow pulse is emitted on lead 17 to SET flip-flop 18 and perform the borrow function as set out above. If, during operation, X changes from being less to being greater than Y then the count will eventually make the transition 9 to 0 at which a pulse is emitted on conductor 19 to switch the flip-flop to the RESET condition removing the add 10 signal from comparator 10 and the subtract 10 signal'from comparator 20.

The system for obtaining the difference of the hundreds digits X and Y is similar to that for the tens and units digits but somewhat simpler'since only two bits are required for each digit. Again, an analogue comparator 30 is provided controlling the operation of a reversible quaternary counter 311via a count-up conductor 33 and a count-down" conductor 34. The output signals E from counter 31 are fed back to comparator 30 via conductors 36. Clock pulses are supplied to counter 31 via conductor 35.

The fixed bias of 180 discussed above is provided to comparators 20 and 30 via conductors 41 and 40 respectively. Conductor 41 is permanently energized to provide a weighted input of 80 to comparator 20 and conductor 40 is permanently energized to provide a weighted input of 100 to comparator 30..

Two further inputs to comparator 20 may be provided via conductors 50 andS-l. These weighted inputs are mutually exclusive and are each of value 60. Their function will be discussed more fully below, they are mentioned at this time to explain the necessity for the more complex carry and borrow provisions between counters 21 and 31.

Due to the bias signals of value 80 and 60 which may both be supplied to comparator 20. the net total of the signals applied to comparator 20 may exceed 200 thus requiring a system for connecting two carry digits to the hundreds stage. Since Y may exceed X plus whatever fixed bias is applied provision must be made for a borrow operation from the hundreds comparator.

Carry flip-flops 60 and 61 are provided together with a borrow flip-flop 28. The SET outputof flip-flop 60 is connected to comparators 20 and 30 via a conductor 66 so that when conductor 66 is energized an additional 100 is added to com parator 30 and subtracted from comparator 20. The SET output offlip-flop 61 is connected to comparators 20 and 30 via a conductor 67 so that when conductor 67 is energized an additional 100 is added to comparator 30 and subtracted from comparator 20. The SET output of flip-flop 28 is connected to comparators 20 and 30 via a conductor 32 which, when energized, subtracts 100 from comparator 30 and adds lOO to comparator 20.

The carry and borrow system is controlled by counter 21 via conductors 27 and'29. When counter 21 makes the transition from 0 to 9 a pulse is emitted on conductor 27 and when the counter makes the transition from 9 to 0 a pulse is emitted on conductor 29. Conductor27 is connected to the RESET input of'fflip-flop 61 and via AND gates 62 and 63 to the SET input of flip-flop 28 and theRESET input of flip-flop 60; respectively. Conductor 29 is connected to the RESET input of flip-flop 28 and via AND gates 64 and 65 to the SET inputs of flip-flops 60fand61, respectively. The remaining inputs of AND gates 62', 63, 64 and 65 are connected to the RESET output of flipflop 60, the RESET output of flip-flop 61, the RESET output oflflip-flop 28 and the SET output of flip-flop 60, respectively.

Theoperation of the carry and borrow system described immediately above is as follows. When the net total ofthe signals applied to comparator 20 is positive a count-up" signal is given on conductor 23 and counter 21 is incremented by one at the occurrence of each clock pulse. If the net total exceeds the counter will pass from'9 to 'O emitting a pulse on lead 29 which, assuming all the flip-flops to have started in the RESET condition, passes through gate 64 to SET flip-flop 60. This adds an additional count of 100 to comparator 30 and subtracts it from comparator 20, lf the net total exceeds 200 counter 21 will continue to count upwards again passing from 9 to 0 and emitting a pulse on conductor'29. This second pulse is routed to SET flip-flop 61 via gate 65,. Gate 65 is open since conductor 68 is connected to the SET. output of flip-flo'p-60. Whenflip-flop 61 is SET conductor 67 is energized to adda further count of 100 to comparator 30, and subtract a further' count of 100 from comparator 20.

If the net total in comparator 20 now decreases this causes counter 20 to count back and, at the first transition from 0 to 9 producing a pulse on conductor 27, flip-flop 61 is RESET, thereby removing the carry of 100 from comparators 20 and 30. Flip-flop 60'is not RESET at this time since gate 63-is not" open until flip-flop 61 has RESET. At the next transition from O to 9 as the counter 21 continues to count downwards flipflop 60 is RESET, removing the carry of 100 from comparators 20 and 30, and restoring the subtractor to its original position.

If the net total in comparator 20-is negative counter 21 will make a further transition from 0 to 9 emitting a pulse on con-' ductor 27 to SET flip-flop 28 via gate 62. Gate 62 is open When the condition set out in relationship (3) applies, that is,

When the condition set out in relationship (3) applies, that is,

then the total error signal will exceed 360, due to the fixed bias of 180. A 360 detector 52 is provided to sense this condition. Detector 52 is responsive to the E digit; the three most significant bits of the E digit and the count-up signal from comparator 30 to emit a pulse on lead 53 when the E signal exceeds 360. This pulse is used to SET a flip-flop 44 via an AND gate 46. The SET output of flip-flop 44' is connected via a conductor 51 to comparators 20 and 30 and, when energized, subtracts 300 from the net count in comparator 30 and 60 from the net count in comparator 20 thereby restoring the E signal to the range O-360 in accordance with equation (4).

if the value of X Y then falls below 180 the E signal will fall below zero. A zero detector 42 is provided to sense this' condition and emit a pulse on lead 43 when it occurs. Lead 43 is connected to the RESET terminal of flip-flop 44 via an 45. The SET output of flip flop 45 is connected viaa conductor 50 to comparators and and, when energized, adds 300 to the net count in comparator 30 and 60 to the net count in comparator 20 thereby restoring the E signal to the range 0- 360 in accordance with equation (6).

E X Y+540 (6) If the value of X Y subsequently exceeds l80 the E signal will exceed 360 thereby triggering the 360 detector 52 and switching flip-flop 45 to the RESET position. AND gate 46 has one input connected to the RESET output of flip-flop 45 and AND gate 47 has one input connected to the RESET output of flip-flop 44 so that either flip-flop can be SET only if the other flip-flop is RESET.

While the described embodiment uses binary coded decimal representation of the angles it will be clear that any 0-form of coding may be used with a suitable alteration in the equipment as will be obvious to one skilled in the art.

lclaim:

l. A digital subtractor responsive to first and second digital signals representing angles in the range 0359 to produce an output signal representative of the difference of said angles or the conjugate of said difference, whichever is smaller, comprising:

subtraction means responsive to said first and second signals to provide the difference thereof;

means connecting said first and second signals to said subtraction means;

fixed bias means connected to said subtraction means to add a fixed digital signal representing 180 thereto; and switchable bias means connected to said subtraction means and responsive to said output signal exceeding or falling short of the range 0-359 to supply an additional signal thereto restoring said output signal tothe range 0-359.

2. A digital subtractor as set out inclaim 1 wherein said switchable bias means comprises:

first bias means responsive to said output signal exceeding 359 to reduce said output signal by 360; and second bias means responsive to said output signal falling below zero to increment said output signal by 360.

3. A digital subtractor as set out in claim 2 wherein said first bias means includes a 360 detector responsive to a portion of said output signal and controlling a first flipflop circuit, said first flip-flop circuit in one of its stable positions supplying a signal representing 360 to said subtraction means, and wherein said second bias means includes a zero detector responsive to a portion of said output signal and said subtraction means and controlling a second flip-flop, said second flipflop circuit in one of its stable positions supplying a signal representing 360 to said subtraction means.

4. A digital subtractor as set out in claim 2 wherein said subtraction means includes first, second and third subtractors responsive to units, tens and hundreds digits, respectively, and

digital interconnecting means between said first and second subtractor and between said second and third subtractor to perform carry and borrow operations.

5. A digital subtractor as set out in claim 4 further including a source of clock pulses and wherein said first, second and third subtractors each consist of an analogue comparator controlling a reversible counter to respond to said clock pulses to indicate the algebraic sum of all inputs to said comparator.

6. A synchronous digital subtractor responsive to first and second digital signals representing angles in the range 0-359 to produce an output signal representative of the difference of said angles or the conjugate of said difference, whichever is smaller, comprising:

a source of clock pulses; first, second and third subtraction means each consisting of an analogue comparator controlling a reversible counter;

means connecting the units, tens and hundreds digits of said first and second digital signals to weighted inputs of the comparators of said first, second and third subtraction means, respectively, so that the reversible counters respond to said clock pulses to count to a number representative of the difference of said first and second signals;

a first flip-flop controlled by the counter of said first subtraction means having one of its stable positions supplying a signal in a positive sense to the input of the comparator of said first subtraction means and in a negative sense to the input of the comparator of said second subtraction means thereby performing a borrow operation between said first and second subtraction means; second, third and fourth flip-flop controlled by the counter of said second subtraction means each having one of its stable positions supplying signals to the comparators of said second and third subtraction means in opposite senses to perform carry and borrow operations between said second and third subtraction means;

fixed bias means adding inputs representing and I00 to the comparators of said second and third subtraction means, respectively;

a zero detector responsive to the count in the counter of said third subtracting means to indicate a count of zero in said last-named counter;

first and second gate means responsive to said zero detector and to the comparator of said third subtracting means to indicate a count below zero in all said counters;

a fifth flip-flop controlled by said first gate means and in its SET position supplying signals to the comparators of said second and third subtracting means to add inputs representing 60 and 300 respectively,

a 360 detector responsive to the count in the counters of said second and third subtracting means and to the comparator of said third subtracting means to indicate a count in excess of 260 in all said counters,

. a sixth flip-flop controlled by said 360 detector and in its SET position supplying signals to the comparators of said second and third subtracting means to decrease the resulting counts by 60 and 300 respectively; and

said fifth flip-flop being RESET by the action of said 360 detector and said sixth flip-flop being RESET by the output of said second gate means. 

